(1) Field of the Invention
The present invention relates to computer systems having a power reduction function, and more particularly to: a computer system including a processor device having an execution mode for receiving a supply of a clock signal and a suspension mode in which the supply of the clock signal is suspended by responding, with a sleep response signal, to a sleep request signal received from an external device; and a method for controlling the computer system.
(2) Description of the Related Art
In recent years, along with a rapid increase of the need for mobile communication appliances such as mobile phones, the need for Large-Scale Integrations (LSI) for the mobile communication appliances has also increased significantly. Further, as the mobile communication appliances become more highly-functioned, it is becoming popular for the LSI of the mobile communication appliances to have a processor capable of performing parallel processing or a multiprocessor having plural processors in a single LSI.
Patent Reference 1, Japanese Unexamined Patent Application Publication No. 11-305887, discloses a method for controlling a microcontroller which does not invalidate processing of a peripheral circuit when switching to a low-power consumption mode. With this controlling method, at first, it is judged whether or not the peripheral circuit is in operation. When it is judged that the peripheral circuit is not in operation, a clock signal for the Central Processing Unit (CPU) and a clock signal for the peripheral circuit are switched to the low-power consumption mode. On the other hand, when it is judged that the peripheral circuit is in operation, the clock signal for the peripheral circuit is switched to the low-power consumption mode after the operation of the peripheral circuit is completed. As a result, this method prevents the processing of the peripheral circuit from being invalidated.
In addition, Patent Reference 2, Japanese Patent No. 3000965, discloses a data processing apparatus which promptly switches from a stand-by mode to a normal operation mode. This data processing apparatus is incorporated in mobile phones and the like and provides a frequency dividing circuit with a frequency division control signal for setting an operating frequency of the clock signal in a halt mode. When a halt instruction is executed and the data processing apparatus switches to the halt mode, it switches the operating frequency of the clock signal, which is to be supplied to the peripheral processing unit, to a low frequency and supplies the clock signal having the switched operating frequency. As a result of this, the power used by the peripheral processing unit is reduced. Besides, when this data processing apparatus switches from the halt mode to the normal operation mode, the frequency of the peripheral processing unit is switched to the normal operation frequency, and therefore, the data processing apparatus can cause the mobile phone to promptly switch from a call stand-by mode to a calling mode.
However, the above described prior arts entail the following problems.
First, with Patent Reference 1, when the microcontroller is making access to a memory or the peripheral circuit, it is not possible to switch to the low-power consumption mode until the access is completed. Even with Patent Reference 2, it is also not possible to switch to the halt mode while the CPU is making access, because the halt instruction cannot be executed until the access is competed. Consequently, this causes a problem that the power consumption cannot be reduced until the access is completed. To put it differently, the time period of the low-power consumption mode or the halt mode is short, which results in a problem that the power consumption cannot be sufficiently reduced.
Second, with Patent Reference 2, a low-frequency clock signal is supplied to the peripheral processing unit in the halt mode, however, when the peripheral processing unit includes a timer or a counter, the time measurement cannot be performed accurately. As a consequence, there is a problem that when the data processing apparatus performs real-time processing, the timing to start the processing is delayed, and thus the processing performance cannot be guaranteed and the real-time processing cannot always be performed accurately.